1. Field of the Invention
The present invention relates to a read/write apparatus for a semiconductor memory device, and more particularly, a read/write control circuit for stabilizing a data write operation.
2. Background of the Related Art
FIG. 1 is a read/write control circuit of a conventional semiconductor memory device. An input buffer 11 compares an externally applied write enable signal WE to a valid signal level, which is preset therein. A write timing generator 12 receives the output signal from the input buffer through an inverter I1 and outputs a write signal. A read timing generator 13 generates a read timing signal in accordance with a row address strobe signal RAS and a column address strobe signal CAS, and outputs a chip enable signal CE in accordance with an output enable signal. An output buffer 14 receives the chip enable signal CE and externally outputs data D and /D applied thereto from the semiconductor memory device in accordance with the chip enable signal CE.
The input buffer 11 includes pull-up transistor PM1 and pull-down transistor NM1 and serves as an inverter to compare the level of the write enable signal WE to a preset threshold voltage Vth (0.8&lt;Vth&lt;2.4 in case of TTL input buffer). When the write enable signal WE has a level lower than the threshold voltage level, the input buffer 11 outputs a high output signal. When the write enable signal WE has a level higher than the threshold voltage level, the input buffer 11 outputs a low output signal.
During a write operation of a semiconductor memory device, the write enable signal WE of a prescribed low level Vi1 is generated, as shown in the beginning portion of FIG. 2C, such that the input buffer 11 outputs a high signal, which is inverted to a low level signal by the inverter I1. The low signal is applied to the write timing generator 12 to output a write signal W, which is transmitted to an internal circuit, thereby writing data in the semiconductor memory device.
During a read operation of the semiconductor memory device, a write enable signal WE of a prescribed high level Vih is applied to the input buffer 11, as shown in the latter portion of FIG. 2C, such that a high level signal is provided by the inverter I1 to the write timing generator 12. As a result, the operation of the write timing generator 12 is stopped, and a write signal W is not generated.
At this time, the row and column address strobe signals RAS and CAS, as shown in FIGS. 2A and 2B, together with the output enable signal OE are applied to the read timing generator 13 to generate the chip enable signal CE, which is logically NANDed with the respective data D and /D by the NAND gates ND1 and ND2. The outputs from the NAND gates ND1 and ND2 passes through the respective inverters I2 and I3. The outputs of the inverters I2 and I3 are applied to the respective gate of a pair of NMOS transistors NM2 and MN3, which are serially connected to each other between a supply potential Vcc and a ground potential Vss. As a result, the output buffer 14 outputs a logic data signal DQi corresponding to the data D.
The ground voltage Vss of the semiconductor memory device is applied via a lead frame, which is connected through a bonding wire to an external ground terminal GND. A coil L in FIG. 1 denotes a parasitic inductance generated by the bonding wire and the lead frame. More importantly, when the level of the output data DQi transits from high to low during a read operation, a large amount of current flows quickly through the pull-down NMOS transistor NM3 of the output buffer 14 to the ground terminal Vss. As a result, the ground voltage Vss bounces due to the inductance coil L, as shown in FIG. 2E.
Therefore, the effective signal level of the input buffer 11, which should maintain a high level Vih for a read operation, is disrupted to dip down below the threshold voltage Vth, and the write enable signal WE transits to a low level for an interim period. The write timing generator 12 performs an inadvertent write operation, thereby resulting in a modification of a memory cell data and causing an operational error.
The above-described write/read control circuit of the conventional semiconductor memory device has various disadvantages. For example, when the output data level transits from a high to a low level during a read operation (FIG. 2E), a large current instantaneously flow through the pull-down NMOS transistor to the ground terminal such that the ground voltage bounces. Accordingly, the write enable signal WE may be erroneously recognized as a low level, thereby leading to a write operation of the memory device and generating an operational error.
To prevent the error in operation, the output terminal of the input buffer 11 is provided with a filter 15, composed of a NAND gate ND3 and a delay unit D having an odd number of inverters therein for blocking short transient signals, as shown in FIG. 3. An erroneous write enable signal caused by the bouncing of the ground voltage is eliminated. However, the filter 15 delays the normal write operation by the delay time period of the filter.